1. Field of the Invention
The invention relates in general to a signal transmitting system, and more particularly, to a signal transmitting system and method and the signal driving device thereof.
2. Description of the Related Art
A large amount of power loss will occur when signals are transmitted via a long transmission line. Since the power consumption is proportional to the square of the voltage during signal transmission, a signal transmitting system is normally used to reduce the voltage of signal at the outputting end first, use a lower voltage level to transmit the signal so as to reduce power loss, and the voltage of the signal is risen to original level at the receiving end.
Referring to FIG. 1, a configuration diagram of a conventional signal transmitting system is shown. The signal transmitting system 100 comprises a conventional signal outputting unit 110 and a signal receiving unit 120. The conventional signal outputting unit 110 receives a first signal S1 then outputs a second signal S2, wherein the second signal S2 has a level lower than the first signal S1 and is substantially of the same phase with the first signal S1. After that, the signal receiving unit 120 receives the second signal S2 and outputs a third signal S3, wherein the third signal S3 is substantially the same with the first signal S1. The voltage of the signal is reduced during transmission and is restored to the original voltage level after the signal at the receiving end.
Referring to FIG. 2, a circuit diagram of a conventional signal transmitting system is shown. Conventional signal outputting unit 110 comprises an inverting device 112 and an inverting device 114. The inverting device 112 is a CMOS inverter according to prior art for receiving a first signal S1 and outputs a first inverted signal S1′, wherein the first inverted signal S1′ and the first signal S1 are of opposite phases. The inverting device 112 comprises an NMOS transistor T1 and a PMOS transistor T2, wherein the source of the PMOS transistor T2 is biased by the main voltage Vh.
The inverting device 114 is a CMOS inverter according to prior art for receiving the first inverted signal S1′ and outputting a second signal S2. The inverting device 114 comprises an NMOS transistor T3 and a PMOS transistor T4, wherein the source of the PMOS transistor T4 is biased by a main voltage VI, the main voltage VI is lower than the first the main voltage Vh. Since the main voltage VI is lower than the main voltage Vh, the second signal S2 and the first signal S1 can have the same phase, while the level of the second signal S2 is lower than that of the first signal S1.
Despite that the above signal transmitting system avoids power loss during transmission, the corresponding time of equivalent resistor and equivalent capacitance of the transmission line 130 still affects the signal transmission speed due to the length of the transmission line 130. Under such circumstances, a MOS transistor with larger power current driving ability is required to promptly increase the transmission line 130 to a target level.
In conventional CMOS inverter 114, since the electron mobility μp of the PMOS is approximately equal to ⅓ of the electron mobility μn of the NMOS, the PMOS transistor will have a lower operating speed and a poorer power current driving ability. For the PMOS transistor to generate a larger power current so as to increase the power current driving ability, the transistor aspect ratio (W/L) must be increased. Consequently, the size of the conventional signal outputting unit 110 becomes larger. How to reduce the size of the signal outputting unit has thus become an imminent challenge to the semiconductor industry.